In digital electronic systems, multiple-bit words are transferred between and within circuits over parallel buses. The buses typically include multiple parallel conducting lines over which signals are transferred. In a typical conventional bus, each bit of a multiple-bit word is transferred over the bus on a single respective parallel conducting line. In parallel systems, all of the bits of a single word are transferred simultaneously across the bus on the parallel lines. Each circuit or system with access to the bus interfaces with the bus via interface circuitry which can include a bus driver circuit for transmitting data signals as well as a receiver circuit for receiving bus signals.
In conventional systems, data and command words are encoded in binary data format, i.e., each bit can assume one of two states and can therefore represent one of two conditions or items of information. This is typically accomplished by setting a voltage on a bus line to one of two possible voltage levels. The bus driver circuitry is capable of applying one of the two voltage levels to the bus according to the desired condition for the data bit being carried by the particular conducting line. The receiver circuit is capable of detecting the applied voltage on the line and converting that voltage to the appropriate data bit. For example, in CMOS systems, the bits are represented by nominal voltage levels of 0 volts and +5 volts. The driver circuitry for each bus line is capable of setting the voltage level of the bus line at either 0 volts or +5 volts, depending on the data bit being represented by the signal transferred over the line.
In some systems, buses are bidirectional. That is, data signals can be transferred across the bus lines in either direction. To accommodate this feature, both ends of the conducting lines include both driver and receiver circuitry.
As systems have become more complex, demand has increased for high rates of data transfer across buses. Two approaches have typically been used to accommodate this increase in demand for higher transfer rates. Buses have been made wider, i.e., provided with an increased number of conducting lines, such that they can carry more parallel data simultaneously. Data transfer rates have also been increased in some systems by increasing the frequency or clock rate at which transfers take place.
Both of these approaches have limits. For example, increasing the number of bus lines increases the physical size of the bus and the associated circuitry, which runs counter to the continuously increasing demand for smaller circuitry and circuit board hardware. Increasing the frequency or clock rate of the system tends to increase power consumption. Therefore, the frequency is limited by, among other things, a maximum allowable or desired power consumption.
Also, prior systems have drawbacks because they require that bus voltages be switched very quickly. Bus capacitances can slow voltage switching, such that the frequency of data transfers is limited. Also, switching voltages on the capacitively coupled bus lines can introduce noise which degrades performance and can increase power consumption.